Various digital signaling protocols have been developed to support communication between integrated circuits in a system such as a mobile device. Examples of such digital signaling protocols include general purpose I/O (GPIO) and universal asynchronous receiver transmitter (UART), serial peripheral interface (SPI), and inter-integrated circuit (I2C). As technology advances, these various digital signaling protocols have been enhanced. For example, the assignee of the present matter has developed a “virtual” GPIO architecture in which a GPIO state machine and interface serializes GPIO data from a processor and transmits the serialized GPIO data over a dedicated transmit pin. Since the processor needs no or minimal software modification in that it may continue to interface though a GPIO interface in a conventional fashion, the transmission of assorted GPIO signals over a dedicated transmit pin instead of over a corresponding plurality of conventional GPIO pins is transparent to the processor. A remote integrated circuit receives the serialized virtual GPIO data over a dedicated receive pin. Each virtual GPIO integrated circuit thus includes at least two pins (a transmit pin and a receive pin). In addition, a clock pin may be provided to synchronize the transmitting and receiving integrated circuits. In other embodiments, no clock pin is utilized such that there are both two-pin and three-pin virtual GPIO embodiments.
Since there are various digital signaling protocol configurations, it is desirable that the particular protocol being implemented be identified during device enumeration. However, existing device enumeration techniques assume that the signaling protocol for the master and slave are homogeneous.
Accordingly, there is a need in the art for improved enumeration techniques that support heterogeneous links and protocols.